The subject invention relates to pulse generators and more particularly, to pulse generators responsive to address transition in a memory circuit.
Address transition detection has been found to be useful in improving the speed-power product for memories, particularly static random access memories (SRAMs). One of the primary uses of address transition detection is to equalize the voltage on pairs of bit lines just prior to sensing data. An equalization pulse is generated in response to detecting an address transition. While the equalization pulse must be of sufficient duration to equalize the bit lines, it is desirable for the equalization pulse to be as short in duration as possible to minimize access time. Accordingly, for a given memory there is an optimum pulse width for the equalization pulse. Consequently it is desirable to be able to set the pulse width for a predetermined duration which is not dependent upon how many address signals change state.
One technique for achieving consistent pulse width is to have a transition detector for each address signal. Each transition detector generates a transition pulse when its respective address signal switches logic states. A multi-input NOR gate receives the transition pulses. The NOR gate discharges a capacitive node which is subsequently charged at a consistent rate when there are no more transition pulses present. The charging occurs through a load of a predetermined resistance to establish a known RC time constant. A detector, such as a conventional buffer or inverter, is used to detect when the node reaches a certain voltage. When the node is initially discharged the equalization pulse is generated. the equalization pulse is terminated when the node reaches the threshold voltage of the detector. The pulse width begins when the first transition pulse occurs and terminates when the node reaches the threshold of the detector.
There are several shortcomings of this approach. The pulse width is longer than necessary when there are several transition signals which occur close together but not simultaneously. The equalization pulse occurs when the first transition pulse occurs but the RC delay does not take effect until the last transition pulse to occur terminates.
Another disadvantage of this approach is the current drain caused by the charging load device and the NOR gate when transition pulses are present. Although the current drain may occur for only a very short time (the duration of a transition pulse) in the case where only one transition pulse occurs or where the occurrence of transition pulses is simultaneous, there are cases where there are very frequent transition pulses. During such a situation the memory is not expected to provide useful data, but the problem is that there will be essentially continuous current flowing through the load device and the NOR gate.
Another shortcoming is that the time delay has several processing variables. The resistance and capacitance variables are expected. Another variable is the threshold voltage of the detector. The equalization pulse is terminated when the node is charged to the threshold voltage of the detector. Because the voltage is intentionally made to rise slowly, process variations in threshold voltage must also be taken into account to ensure having at least the minimum required pulse width to achieve bit line equalization.